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general description the max2150 is a complete wideband direct upconver- sion quadrature modulator ic incorporating a 28-bit sigma-delta fractional-n synthesizer. the device is tar- geted for applications in the 700mhz to 2300mhz fre- quency range. the super-high-resolution sigma-delta fractional-n syn- thesizer is capable of better than 50mhz resolution when used with a 10mhz reference. other features: fully differential i/q modulation inputs, an internal lo buffer, and a 50 wideband output driver amplifier. a standard 3-wire interface is provided for synthesizer programming and overall device configuration. an on- chip low-noise crystal oscillator amplifier is also includ- ed and can be configured as a buffer when an external reference oscillator is used. the device typically achieves 34dbc of carrier and side- band suppression at a -1dbm output level. the wide- band, internally matched rf output can also be disabled while the synthesizer and 3-wire bus remain powered up for continuous programming. the device consumes 72ma from a single +3.0v sup- ply and is packaged in an ultra-compact 28-pin qfn package (5mm ? 5mm) with an exposed pad. applications wireless broadband satellite uplink lmds wireless base station features ? single voltage supply (2.7v to 3.6v) ? 75mhz 3db i/q input bandwidth ? wideband 50 rf output: 700mhz to 2300mhz ? ultra-fine frequency resolution: 100mhz ? high reference frequency for fast-switching applications ? ultra-low phase noise ? low spurious and reference emissions ? -1dbm rms output power ? 60db rf muting control ? 34dbc typical carrier suppression ? 34dbc typical sideband suppression ? software- and hardware-controlled shutdown modes max2150 wideband i/q modulator with sigma-delta fractional-n synthesizer ________________________________________________________________ maxim integrated products 1 rfout n.c. n.c. txen vcc_pa vcc_rf 4 1 2 5 6 7 28 27 26 25 24 23 22 15 16 17 18 19 20 21 max2150 ?mod 90 0 programming and control clk data synen qfn oscin vcc_xtal i+ q+ i- q- bufout bufen lo+ lo- vcc_lo vcc_d vcc_a chp vcc_chp lock vcc_sd 1/n 1/r pfd chp en shdn 8 9 10 11 12 13 14 3 pin configuration/ functional diagram ordering information 19-2389; rev 4; 6/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max2150eti -40c to +85c 28 tqfn-ep* max2150eti+ -40c to +85c 28 tqfn-ep* * ep = exposed paddle. + denotes lead-free package.
max2150 wideband i/q modulator with sigma-delta fractional-n synthesizer 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ...........................................................-0.3v to +6.0v rf signals: lo+, lo-, oscin ........................................+10dbm i+ to i-, q+ to q-.......................................................................2v lo+, lo-, i+, i-, q+, q-, bufen, txen, clk, data, en , synen, oscin, oscout, bufout, chp, shdn, lock, v cc _cp to gnd..............-0.3v to (v cc + 0.3v) digital input current .........................................................?0ma short-circuit duration rfout, bufout, oscout, lock, chp...........................................................................10s continuous power dissipation 28-pin tqfn (t a = +70?)..................................................2w (derate 28.5mw/? above +70?) operating temperature range ...........................-40? to +85? junction temperature range ..........................................+150? storage temperature.........................................-65? to +150? lead temperature (soldering 10s) ..................................+300? dc electrical characteristics (max2150 ev kit. v cc = +2.7v to +3.6v, gnd = 0v, shdn = pllen = txen = high, bufen= low. no ac input signals. rfout and bufout output ports are terminated in 50 . t a = -40? to +85?. typical values are at v cc = +3v, t a = +25?, unless otherwise noted.) (note 1) parameter conditions min typ max units supply supply voltage 2.7 3 3.6 v tx mode, shdn = pllen = txen = high bufen = low 72 107 synth mode, shdn = pllen = high, txen = bufen = low 25 38 supply current mod mode, shdn = txen = high, synen = bufen = low 46 69 ma lo buffer supply current additional current in all modes for bufen = high 3.3 5.5 ma hw_shdn mode, shdn = low 0.3 600 shutdown supply current sw_shdn mode, pwdn bit at logic low 35 600 ? control input/outputs ( shdn , txen, synen, bufen) input logic high 2v input logic low 0.5 v input logic high current 1a input logic low current -1 ? lock detect high (locked) 2 v lock d etect low ( u nl ocked ) 0.5 v power-up time mod mode 25 ? power-down time mod mode 1 s 3-wire control input (clk, data, en ) input logic high v cc - 0.5 v input logic low 0.5 v input logic high current 1a input logic low current -1 ? caution! esd sensitive device
max2150 wideband i/q modulator with sigma-delta fractional-n synthesizer _______________________________________________________________________________________ 3 parameter conditions min typ max units modulation input bw (-1db) 26 i/q input bandwidth bw (-3db) 75 mhz i/q differential input level assumes a sine-wave input to achieve the rfout output power specified below 1v p-p i/q dc input resistance 200 k i/q common-mode input range (note 2) 1.5 1.6 1.7 v rf output frequency range 700 2300 mhz txen = high, f rf = 1750mhz -7 -1 output power txen = low, f rf = 1750mhz -60 dbm output 1db compression point 1 dbm output ip3 14 dbm carrier suppression f rf = 1750mhz 34 dbc sideband suppression f lo - f i/q , f rf = 1750mhz 25 34 dbc rf output noise floor f offset > 40mhz (note 2) -148 -143 dbm/hz output return loss (note 3) -9 db lo input/output frequency range 700 2300 mhz lo input power (note 2) -12 -10 -7 dbm lo input return loss f lo =2000mhz -15 db lo buffer output level bufen = high (note 2) -14 -9.5 dbm sigma-delta fractional-n synthesizer system requirements frequency range (note 2) 700 2300 mhz phase-detector input-referred phase noise floor f comp = f ref = 20mhz, cp0 = cp1 = cpx = 1 (note 4) -138 dbc/hz in-loop spurious emissions f lo = 1740.005mhz, f comp = f ref = 20mhz, cp0 = cp1 = cpx = 1 (note 5) -40 dbc main divider and phase detector minimum fractional-n step size f comp / 2 28 phase-detector comparison frequency 20 30 mhz maximum n division 251 minimum n division 35 ac electrical characteristics (max2150 ev kit. v cc = +2.7v to +3.6v, shdn = pllen = txen = high, bufen =low. input i/q signals: f i/q = 500khz, v i/q = 1v p-p . i+, q+ single-ended input, driven from ac-coupled source. i-, q- single-ended inputs are ac-coupled to gnd. rfout and bufout output ports are terminated in 50 loads. f lo =1750mhz, p lo = -10dbm, typical values are at v cc = +3v, t a = +25?, unless other- wise noted.) (note 1)
max2150 wideband i/q modulator with sigma-delta fractional-n synthesizer 4 _______________________________________________________________________________________ parameter conditions min typ max units reference oscillator and divider input frequency range 10 50 mhz ac-coupled input sensitivity ac-coupled, single ended (note 2) 0.4 2.3 v p-p reference division ratio (notes 2, 6) 1 4 charge-pump output cpx = 0 0.12 0.17 0.22 cp1, cp0 = 00 cpx = 1 0.23 0.34 0.44 cpx = 0 0.23 0.35 0.46 cp1, cp0 = 01 cpx = 1 0.47 0.67 0.88 cpx = 0 0.36 0.52 0.68 cp1, cp0 = 10 cpx = 1 0.70 1.00 1.30 cpx = 0 0.48 0.69 0.90 charge-pump current (note 7) cp1, cp0 = 11 cpx = 1 0.91 1.31 1.70 ma charge-pump voltage compliance sink/source currents match within ?% 0.5 v cc - 0.5 v ac electrical characteristics (continued) (max2150 ev kit. v cc = +2.7v to +3.6v, shdn = pllen = txen = high, bufen = low. input i/q signals: f i/q = 500khz, v i/q = 1v p-p . i+, q+ single-ended input, driven from ac-coupled source. i-, q- single-ended inputs are ac-coupled to gnd. rfout and bufout output ports are terminated in 50 loads. f lo =1750mhz, p lo = -10dbm, typical values are at v cc = +3v, t a = +25?, unless other- wise noted.) (note 1) note 1: parameters are guaranteed by production testing at +25 c and +85 c. minimum and maximum values over the tempera- ture and supply voltage range are guaranteed by design and characterization. note 2: guaranteed by design and characterization. note 3: measured with max2150 ev kit. note 4: measured with an on-chip crystal oscillator. note 5: in-loop spurious emissions occur when synthesizing a frequency at an integer multiple of the comparison frequency with fractional offset within the pll loop bw. note 6: if an on-chip oscillator is used, a fundamental tone crystal is needed. note 7: minimum and maximum values at cpx = 1 are guaranteed by production testing. values at cpx = 0 are guaranteed by design and characterization.
max2150 wideband i/q modulator with sigma-delta fractional-n synthesizer _______________________________________________________________________________________ 5 supply current vs. supply voltage max2150 toc01 supply voltage (v) supply current (ma) 3.3 3.0 20 40 60 80 +85 c +25 c -40 c tx mode 100 0 2.7 3.6 modulation output power vs. frequency max2150 toc02 frequency (mhz) modulation output power (dbm) 1900 1500 1100 -10 -8 -6 -4 -2 0 2 4 -12 700 2300 +85 c +25 c -40 c txen = high modulation output power vs. frequency max2150 toc03 frequency (mhz) modulation output power (dbm) 1900 1500 1100 -67 -64 -61 -58 -55 -70 700 2300 +85 c +25 c -40 c txen = low output power vs. lo power max2150 toc04 lo power (dbm) output power (dbm) 11 10 8 9 -1.9 -1.8 -1.7 -1.6 -1.5 -1.4 -1.3 -1.2 -1.1 -1.0 -2.0 712 carrier and sideband suppressions vs. lo power max2150 toc05 lo power (dbm) carrier and sideband suppressions (db) 11 10 9 8 33 34 35 36 37 38 32 712 sideband suppression carrier suppression modulator output power vs. i/q input level max2150 toc06 i/q input level (mv) modulator output power (dbm) 1400 1200 1000 800 600 400 200 -20 -16 -12 -8 -4 0 4 -24 0 -40 c +25 c +85 c typical operating characteristics (max2150 ev kit. v cc = +3v, shdn = pllen = txen = high, bufen = low. input i/q signals: f i/q = 500khz, v i/q = 1v p-p . i+, q+ sin- gle-ended input, driven from ac-coupled source. i-, q- single-ended inputs are ac-coupled to gnd. rfout and bufout output ports are terminated in 50 loads. f lo =1750mhz, p lo = -10dbm, t a = +25?, unless otherwise noted.)
max2150 wideband i/q modulator with sigma-delta fractional-n synthesizer 6 _______________________________________________________________________________________ modulator output ip3 vs. v cc max2150 toc07 v cc (v) modulator output ip3 (dbm) 3.3 3.0 11 12 13 14 15 16 10 2.7 3.6 -40 c +25 c +85 c modulator output p1db vs. v cc max2150 toc08 v cc (v) modulator output p1db (dbm) 3.3 3.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 -1.0 2.7 3.6 -40 c +25 c +85 c lo port input return loss vs. frequency max2150 toc09 frequency (mhz) lo port return loss (db) 1900 1500 1100 -25 -20 -15 -10 -5 0 -30 700 2300 bufout port return loss vs. frequency max2150 toc10 frequency (mhz) bufout port return loss (db) 1900 1500 1100 -25 -20 -15 -10 -5 0 -30 700 2300 lo buffer output power vs. frequency max2150 toc11 frequency (mhz) lo buffer output power (dbm) 1900 1500 1100 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -14 700 2300 -40 c +25 c +85 c bufen = high lo buffer output power vs. frequency max2150 toc12 frequency (mhz) lo buffer output power (dbm) 1900 1500 1100 -52 -49 -46 -43 -40 -55 700 2300 -40 c +25 c +85 c bufen = low typical operating characteristics (continued) (max2150 ev kit. v cc = +3v, shdn = pllen = txen = high, bufen = low. input i/q signals: f i/q = 500khz, v i/q = 1v p-p . i+, q+ single-ended input, driven from ac-coupled source. i-, q- single-ended inputs are ac-coupled to gnd. rfout and bufout output ports are terminated in 50 loads. f lo =1750mhz, p lo = -10dbm, t a = +25?, unless otherwise noted.)
max2150 wideband i/q modulator with sigma-delta fractional-n synthesizer _______________________________________________________________________________________ 7 oscin port sensitivity (synthesizer) vs. frequency max2150 toc13 frequency (mhz) oscin port sensitivity (v) 45 40 35 30 25 20 15 1 2 3 4 5 6 0 0.10 0.20 0.30 0.40 0.50 0.60 0 10 50 -40 c -40 c +25 c +25 c +85 c +85 c oscin impedance vs. frequency max2150 toc14 frequency (mhz) oscin port impedance ( ) 45 40 30 35 20 25 15 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 -1000 10 50 imaginary real synthesizer phase noise max2150 toc15 span = 20khz center = 1.75mhz -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -8.5dbm n/c = -99dbc/hz i/q modulator output spurs max2150 toc16 span = 2 mhz center = 1.75 ghz -100 -90 -80 -70 -60 1 avg -50 -40 -30 -20 -10 0 carrier suppression -34dbc sideband suppression -36dbc typical operating characteristics (continued) (max2150 ev kit. v cc = +3v, shdn = pllen = txen = high, bufen = low. input i/q signals: f i/q = 500khz, v i/q = 1v p-p . i+, q+ single-ended input, driven from ac-coupled source. i-, q- single-ended inputs are ac-coupled to gnd. rfout and bufout output ports are terminated in 50 loads. f lo =1750mhz, p lo = -10dbm, t a = +25?, unless otherwise noted.)
max2150 wideband i/q modulator with sigma-delta fractional-n synthesizer 8 _______________________________________________________________________________________ pin description pin name function 1 txen modulator enable input. set txen low to inhibit the rf and modulator circuits. this mode can be used for quiet frequency synthesis. 2 vcc_pa supply voltage input for rfout output driver circuits. bypass as close to the pin as possible. the bypass capacitor should not share ground vias with other branches. 3 rfout modulator rf output. this is a wideband, internally matched 50 output. a dc-blocking capacitor is required. 4, 5 n.c. do not connect. (these pins must be left floating.) 6 lock lock status of the pll. a static logic-level high indicates that the pll is in the locked condition. 7 vcc_sd supply voltage input for sigma-delta modulator circuits. bypass as close to the pin as possible. the bypass capacitor should not share ground vias with other branches. 8, 9, 10 clk, data, en input pins from 3-wire serial bus. an rc lowpass filter on each of these pins can be used to reduce digital noise. 11 shdn shutdown control. set shdn low to disable all internal circuits for lowest power consumption. an rc lowpass filter can be used to reduce digital noise. 12 synen synthesizer enable input. set synth low to disable the internal frequency synthesizer. an rc lowpass filter can be used to reduce digital noise. 13 oscin reference oscillator input. connect a parallel, resonant, fundamental-tone crystal between this pin and ground to facilitate a crystal oscillator circuit. for applications with an external reference oscillator, the oscin input can be driven through a large-value series capacitor. 14 vcc_xtal supply voltage input for crystal oscillator. bypass as close to the pin as possible. the bypass capacitor should not share ground vias with other branches. 15 vcc_chp supply voltage input for charge pump. bypass as close to the pin as possible. the bypass capacitor should not share ground vias with other branches. 16 chp high-impedance charge-pump output. connect to the tune input of the vco through the pll loop filter. keep the line from this pin to the tune input as short as possible to prevent spurious pickup, and connect the loop filter as close to the tune input as possible. 17 vcc_a supply voltage input for pll. bypass as close to the pin as possible. the bypass capacitor should not share ground vias with other branches. 18 vcc_d supply voltage input for pll. bypass as close to the pin as possible. the bypass capacitor should not share ground vias with other branches. 19 vcc_lo supply voltage input for internal lo circuits. bypass as close to the pin as possible. the bypass capacitor should not share ground vias with other branches. 20, 21 lo-, lo+ differential local-oscillator input. these inputs require dc-blocking capacitors. the lo can be applied with a single-ended input to the lo+/lo- pin. in this mode, the other pin should be ac-grounded. 22 bufout buffered lo output. internally matched to 50 , requires a dc-blocking capacitor. 23 bufen lo output buffer amplifier enable. set bufen high to enable the on-chip output lo buffer for driving external circuits. an rc lowpass filter can be used to reduce digital noise. 24, 25 q-, q+ differential q-channel baseband inputs to the modulator. these pins connect directly to the bases of a differential pair and require an external common-mode bias voltage of 1.6v.
detailed description internally, the max2150 includes a broadband i/q modulator, internally matched broadband output driver amplifier, fine-resolution fractional-n frequency synthe- sizer, an lo buffer amplifier, and an on-chip low-noise crystal oscillator circuit. a simple 3-wire interface is provided for synthesizer programming and device configuration and control. independent hardware and software power-down con- trol of the i/q modulator, frequency synthesizer, and lo buffer amplifier is provided, as well as the ability to shut down the entire chip. i/q modulator the max2150 modulator is composed of a pair of matched double-balanced mixers, a broadband pas- sive lo quadrature generator, and a summing amplifi- er. the mixers accept differential i/q baseband signals that directly modulate the internal 0 and 90 lo sig- nals applied to the i/q mixers. an external lo source drives an internal lo quadrature generator that shifts the phase of the lo signal applied to the q mixer by 90 relative to the lo signal applied to the i-channel mixer. the modulated output of the i/q mixers is summed together, and the undesired sideband is sup- pressed. the i+, i-, q+, and q- input ports feature high-linearity buffer amplifiers with a typical -3db bandwidth of 75mhz and accept differential input voltages up to 1v p-p . the ports require external biasing and have an input common-mode requirement of 1.6v. for single- ended operation, bypass the i and q ports to ground. see the typical application circuit for recommended component values. the broadband output driver amplifier is matched on chip across the entire operating frequency range and requires an output dc-blocking capacitor. for optimum performance, the output match can be improved with simple l-section and/or pi-section matching networks. always ensure that dc blocking is provided, because internal bias voltages are present at this output. the modulator can be shut down with both hardware (pin 1) and software (te bit). this mode is useful for quiet synthesizer programming or to mute the rf out- put signal. the hardware pin and software bits must be set to logic-1 to enable the modulator. if the hardware pin or software bit is set to logic-0, or if both are set to logic-0, the modulator is disabled. lo buffer amplifier the broadband buffer amplifier output is internally matched and requires a dc-blocking capacitor to iso- late on-chip bias voltages. power-down of the lo buffer can be controlled by both bufen (pin 23), as well as bufen by software by setting the bufen (be) bit through the 3-wire interface. the hardware pin and the software bit must be a logic-1 to enable the buffer. if the hardware or software bit is set to logic-0, the lo buffer is disabled. frequency synthesizer the max2150 features an internal 28-bit sigma-delta frequency synthesizer. this architecture enables the use of very high (30mhz) comparison frequencies, which significantly reduces the in-loop phase noise as a result of reduced division ratios. the high comparison frequency also allows significantly increased pll bandwidths for very fast switching speed applications. divider programming the max2150 frequency programming is determined as follows. the overall division ratio (d) has an integer value (n), as well as a fractional component (f): d = n.f = n +f / 2 28 the n and f values are encoded as straight binary numbers. determination of these values is illustrated by the following example: f lo = 1721.125mhz, f comp = 20mhz then: d = 1721.125 / 20 = 86.05625 therefore: n = 86 and f = 0.05625 x 2 28 = 15,099,494 max2150 wideband i/q modulator with sigma-delta fractional-n synthesizer _______________________________________________________________________________________ 9 pin description (continued) pin name function 26, 27 i-, i+ differential i-channel baseband inputs to the modulator. these pins connect directly to the bases of a differential pair and require an external common-mode bias voltage of 1.6v. 28 vcc_rf supply voltage input for rf circuits. bypass as close to pin as possible. the bypass capacitor should not share ground vias with other branches. exposed pad ground
max2150 converting each to binary representation results in the following: n register = 86 = 0101,0110 f register value = 0000,1110,0110,0110,0110,0110,0110 the f-register value is then split between an upper 14 bits and a lower 14 bits as follows: upper 14 bits + address 00 = 0000,1110,0110,0100 lower 14 bits + address 01 = 1001,1001,1001,1001 synthesizer shutdown the synthesizer can be disabled by setting synen (pin 12) to a logic low. this mode is useful when an external frequency synthesizer is employed. applications information serial interface and register definition 3-wire interface and registers the max2150 is programmed through a simple 3-wire (clk, data, en ) interface. the programming data is contained within 16-bit words loaded into four unique address locations. each location contains pro- gramming information for setting operational modes and device configuration. two words (address 00, 01) control the fractional divide number in the sigma-delta synthesizer. the third word (address 10) sets the inte- ger divide value, reference divide value, charge-pump current, and charge-pump compensation dac settings. the fourth and final word (address 11) contains various device configuration registers and test registers, as well as additional charge-pump compensation regis- ters. see tables 1 through 11 for details. 3-wire interface timing diagram figure 1 shows the programming logic. the 16-bit shift register is programmed by clocking in data at the rising edge of clk. pulling enable low allows data to be clocked into the shift register; pulling enable high loads the register addressed. fractional spurs when synthesizing a frequency that is an integer multi- ple of the reference divider and having a fractional off- set with a value less than the pll filter bandwidth, fractional spurs can be observed at a typical level of -40dbc. for example, to synthesize 1640.005mhz when using a 20mhz reference and a pll bandwidth of 25khz, spurious products offset from the lo by 5khz can be observed. the 1640mhz is an integer multiple of 20mhz, and the fractional offset of 5khz is within the pll bandwidth. it is possible to avoid the above-mentioned spurious products by using two reference oscillators with slightly offset frequencies or by using a higher reference fre- quency and changing the comparison frequency of the reference divider. crystal oscillator the max2150 includes a simple-to-use on-chip low- noise reference oscillator circuit. the oscillator is formed by connecting a fundamental mode parallel res- onant crystal from oscin to ground. the oscillator cir- cuit is useful from 10mhz to 50mhz. the phase noise of the max2150 can be improved by using a precision high-frequency external reference oscillator (tcxo). the external oscillator is connected through a dc-blocking capacitor directly to the oscin pin. layout considerations a properly designed pc board is an essential part of any rf circuit. a ground plane is essential. keep rf signal lines as short as possible to reduce losses, radi- ation, and inductance. the exposed pad on the under- side of the max2150 must be adequately grounded by ensuring that the exposed paddle of the device pack- age is soldered evenly to the board ground plane. use multiple, low-inductance vias to ground the exposed paddle. wideband i/q modulator with sigma-delta fractional-n synthesizer 10 ______________________________________________________________________________________ t cs t ch t cwl t cwh data clk en t es b19 (msb) b18 b0 a3 a1 a0 (lsb) t cs > 50ns t ch > 10ns t cwh > 50ns t es > 50ns t cwl > 50ns t ew > 50ns t ew figure 1. 3-wire interface timing diagram
max2150 wideband i/q modulator with sigma-delta fractional-n synthesizer ______________________________________________________________________________________ 11 r1 r0 reference divide value 00 1 01 2 10 3 11 4 table 2. reference divider n7 n6 n5 n4 n3 n2 n1 n0 integer divide value 0 0100011 35 0 0100100 36 1 1111010 250 1 1111011 251 table 3. integer divider-n* f27 f26 f25 f24 f23 f22 f21 f20 f19 f18 f17 f16 f15 f14 00000000000000 00000000000000 11111111111111 table 4. fractional divider-f (upper 14 bits) f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 integer divide value 00000000000000 1 00000000000001 2 11111111111110 268435454 11111111111111 268435455 table 5. fractional divider-f (lower 14 bits) *n divider is limited to 35 n 251. table 1. register tables msb shift register data lsb address upper (msbs) fractional divider value (f) 14 bits (default = 8192, 10000000000000) address 27 26 25 24 23 22 21 20 19 18 17 16 15 14 0 0 lower (lsbs) fractional divider value (f)14 bits (default 0 dec, 00000000000000 address 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 r divider default = 00 cp bleed default = 00 cp current default = 11 integer divide value (n) 8 bits default = 177 dec address r1 r0 lin1 lin0 cp1 cp0 7 6 5 4 3 2 1 0 1 0 reset delay default = 00 test registers 6 bits default = 0 dec control register 6 bits default = 15 dec address bl1 bl0 t5 t4 t3 t2 t1 t0 int pd te be xx cpx 1 1
max2150 power-supply (v cc ) bypassing proper voltage-supply bypassing is essential to reduce the spurious emissions mentioned above. it is recom- mended that each v cc pin be bypassed independently and share no common vias with any other ground con- nection. see the typical operating circuit for suggest- ed bypass component values. wideband i/q modulator with sigma-delta fractional-n synthesizer 12 ______________________________________________________________________________________ bit id bit name pwr-up state bit location 0 = lsb function cpx cp_mult 1 0 a logic high doubles the charge pump current selected through registers cp1 and cp0. logic low sets the charge-pump current to the value selected by registers cp1 and cp0. xx xx xx 1 unused. be bufen 1 2 high enables the vco buffer. low disables this output. te txen 1 3 low enables sw_mute mode, which shuts down the rf circuits while leaving the 3-wire interface, register, and pll circuits active. pd pwdn 0 4 low enables register-based shutdown. this mode shuts down all circuits except the 3-wire interface and internal registers. int int_mode 0 5 logic high disables the sigma-delta modulator. logic low enables the sigma-delta modulator for normal operation. table 6. control register hw pins software control bits mode shdn txen synen bufen pwdn txen bufen description tx h h h h/l h h h/l all circuits active. mod h h l h/l h h h/l modulator circuits active. synthesizer blocks disabled. mode is used with external pll circuit. synth h l h h/l h x h/l serial interface and synthesizer blocks active. rf and modulator blocks disabled. mode is used to gate rf on/off with external logic control. sw_mute h h h h/l h l h/l serial interface and synthesizer blocks all active. modulator blocks disabled. mode is used to gate rf on/off with software control. hw_shdn l x x x x x x all circuits disabled. lowest current mode of operation. sw_shdn h x x x l x x serial interface and registers active, all other circuits inactive regardless of the state of the hw pins with the exception of hw_shdn. table 7. device modes
max2150 wideband i/q modulator with sigma-delta fractional-n synthesizer ______________________________________________________________________________________ 13 txen pin bit tx mode 0 0 tx off 0 1 tx off 1 0 tx off 1 1 tx enabled table 8. txen pin and software bit definitions bufen pin bit buf mode 0 0 buffer off 0 1 buffer off 1 0 buffer off 1 1 buffer on table 11. bufen pin and software bit definitions cpx cp1 cp0 i cp (?) 0 0 0 170 0 0 1 350 0 1 0 520 0 1 1 690 1 0 0 340 1 0 1 670 1 1 0 1000 1 1 1 1310 table 9. charge-pump registers test mode t5 t4 t3 t2 t1 t0 test pin normal operating mode 000000 charge pump forced to source icp 000001 cp charge pump forced to sink icp 000010 cp reference divider output 0 1 0 0 0 0 lock main divider output 0 1 1 0 0 0 lock table 10. test register definition (default 0 dec)* * all other logic states are undefined. chip information transistor count: 16,321 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 28 tqfn-ep t2855-3 21-0140
max2150 wideband i/q modulator with sigma-delta fractional-n synthesizer 14 ______________________________________________________________________________________ max2150 vcc vcc vcc vcc vcc gnd j6 j7 c25 1 f c31 0.1 f r29 open c3 0.1 f c17 100pf c18 0.1 f 2 v cc _pa 1 txen 3 rfout 4 test2 c16 open c15 open r13 0 j8 rfout j16 5 test1 j17 7 v cc _sd vccsd 6 lock lock j20 vcc vcc c14 100pf c27 1.0 f clk 8 data 9 en 10 j10? j10? shdn 11 j10?3 synen 12 oscin v cc _xtal 13 14 15 j10?7 j10?9 j10?5 j10? j10?1 j10? j10? j10? j10? j10?2 j10?6 j10?8 j10?0 j10?4 j10? j10?0 j10? c37 0.1 f c36 0.1 f l1 open en jump_pad lock clk enn data filtvcc shdnn txen synen vcosel shdn c30 0.1 f j18 refl in r18 0 y1 c13 100pf c21 0.1 f vcc vcc vcc vcc_vco c9 100pf c19 0.1 f v cc _chp 16 chp 17 v cc _a c22 6800pf c24 680pf c26 470pf c35 100pf c34 0.1 f r23 245 c23 .068 f r24 1.1k r25 1.1k r35 open tuneout vtune_out 1 2 3 6 5 4 vt gnd vcc vsw gnd out gnd gnd 7 8 j5 j11 j19 gnd vccvco u2 vc3r0a230967/ 1750b350fuji c10 100pf vcc 18 v cc _d c4 100pf vcc 19 v cc _lo 20 lo- c12 100pf c11 100pf c8 22pf j15 lon 21 lo+ c7 open j14 lo c5 open c6 open j13 bufout c32 0.1 f c33 0.1 f c20 0.1 f r34 3.3k r33 3.3k r32 3.3k r31 3.3k c28 0.1 f dcin r1 open r2 open r3 open r4 open j1 31-5239-52rfx c50 0.1 f j2 31-5239-52rfx c52 0.1 f c2 100pf v cc _rf 28 i+ 27 i- 26 q+ 25 q- 24 bufen 23 bufout 22 iin qn q c1 0.1 f bufen vcc r12 0 u1 typical operating circuit
max2150 wideband i/q modulator with sigma-delta fractional-n synthesizer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 4 6/08 updated table in package information 13

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